Memory devices are widely used for data storage in electronic devices, such as digital cameras, cellular phones and other portable storage media. Memory can generally be characterized as either volatile or non-volatile. Volatile memory, for example, most types of random access memory (RAM), requires constant power to maintain stored information. A non-volatile memory device is capable of retaining stored information even when power to the memory device is turned off. One example of non-volatile memory is resistive memory cells, in which data is stored in memory cells by structurally or chemically changing a physical property of the memory cells in response to applied programming voltages, which in turn change cell resistance. A variable resistance material whose resistance changes according to its material phase is referred to as a phase-change material.
A particular example of a resistive memory cell using a phase-change material is a phase-change random access memory (PCRAM). In a PCRAM, the memory state is defined as either ‘0’ or ‘1’, due to a change in the phase of the phase-change material between a high resistance amorphous phase and a low resistance crystalline phase (or vice versa). One example of such phase-change materials is chalcogenide materials, which are alloys of Group VI elements of the periodic table, such as Te or Se. A specific chalcogenide currently used in rewriteable compact discs (“CD-RWs”) is Ge2Sb2Te5. In addition to having valuable optical properties that are utilized in CD-RW discs, Ge2Sb2Te5 also has desirable physical properties as a variable resistance material. Various other combinations of Ge, Sb and Te may be used as variable resistance materials and are herein collectively referred to as “GST” materials.
A typical memory device includes a memory array along with its peripheral circuitry. A simplified diagram of a typical memory device 1400 is shown in FIG. 1. Memory device 1400 includes an array of memory bits 1315 arranged in rows and columns (such that each memory bit 1315 in the array may be uniquely identified). The memory bits 1315 are each connected to a row decoder 1460 by a plurality of respective word lines 1430 and to a column decoder 1450 by a plurality of respective cell select lines 1420. The row and column decoders 1460, 1450 and other electronics necessary for operating the memory device make up the peripheral circuitry of the memory device 1400. Each memory bit 1315 in the array includes a memory element (e.g., phase-change material) 220 and an access device 200.
Traditional memory access devices have been planar in nature, meaning that the access devices are formed layer by layer within the plane of the underlying structure (e.g., a substrate that is a base material and layers formed on the surface of the substrate). The access devices are formed within these layers so that the resulting devices are also laid out in a planar arrangement. As a specific example, a planar field-effect transistor (“FET”) is a FET with a conductive channel that is within the layers of the underlying structure. Planar access devices have a relatively large footprint since area is required for source and drain regions and associated contacts as well as isolation between the contacts.
Recently, non-planar access devices have been used as alternatives to planar devices. Non-planar access devices are access devices that are not flat or planar and can be oriented in a vertical direction from a substrate. These devices can include raised portions that extend above the planar surface of the underlying structure. The thin vertical structure results in significant space savings over traditional planar access devices. Vertical transistors are also superior with respect to leakage and drive current as compared to planar transistors or p/n diodes with similar physical dimensions. Specifically, vertical transistors have reduced leakage and higher drive current as compared to other available transistor options.
FIG. 2 illustrates an example of a vertical FET (VFET) 100. The WET 100 includes a thin vertical fin or mesa 120 through which current flows vertically between a source 130 and a drain 140. The mesa 120 extends above a substrate 115. A gate 150 is formed along a sidewall of the mesa 120. Gates 150 are separated from the sidewalls of the mesa 120 by thin gate insulators 155 such as a gate oxide. The thin gate insulators 155 are L-shaped in order to insulate the gates 150 from contact with the mesas 120 and the substrate or any conductor on the substrate. When an appropriate bias is applied to one or more of the gates 150, current flows vertically through the channel 125 from the source 130 to the drain 140.
As the size of electronic devices is becoming increasingly smaller, vertical transistors, such as that shown in FIG. 2, are becoming popular for use as a selection device for memory devices (such as phase-change memory devices) having smaller sizes (e.g., smaller than 22 nm). An example memory access device 200 is shown in FIG. 3A and a schematic diagram is shown in FIG. 3B. In FIG. 3A, memory cell 220 is electrically coupled to the VFET device 200. The memory cell 220 includes a top electrode 222 and a bottom electrode 224. The bottom electrode 224 is coupled to a contact 240 for the drain 140. The source 130 is coupled to a contact 230. Upon appropriate biasing of the source contact 230, the gate 150 and the top electrode 222, the VFET 200 is turned “on” and current flows through the channel 125 and memory cell 220. With appropriate biasing, the current flowing through the memory cell 220 is strong enough to be used as a programming or reset current for the memory cell 220.
However, in order to facilitate the production of the cell module and subsequent back-end-of-line (BEOL) production (e.g., when individual devices get interconnected with wiring on the wafer), it is preferred that these vertical transistors (which are formed above the substrate rather than within it) are integrated into the memory array in such a way that the array portion of the memory device has a top surface that is planar with the peripheral circuit transistor structures (hereinafter “periphery”) of the memory device without any step height between the array and the periphery.
Accordingly, there exists a need for methods for forming vertical transistors with self-aligned contacts that results in the periphery and array portion of the memory cell being planar (or nearly planar) with each other.